Random and deterministic test generation methods, plus sequential circuit test generation.

The text treats testing and testability as integral parts of the digital design process rather than afterthoughts.

Scan architectures, RT-level scan design, and Boundary Scan (JTAG).

This book is widely used as a primary text in and Design for Testability courses. More information can be found at Springer Nature or through retailers like Amazon .

The material is structured into two main parts: developing test environments and implementing testable hardware. Key Topics Covered

A distinguishing feature is the extensive use of the Verilog Programming Language Interface (PLI) . This allows for a mixed hardware/software environment where users can develop "virtual testers" to evaluate complex test strategies.